In contemporary high-speed serial data communications, a duplex high-speed serial (HSS) communication link is typically implemented by an integrated circuit (“IC” or “chip”) that includes at least one pair of a serializer (transmitter) and a deserializer (receiver) on the same chip. Such elements can also be combined in a core, referred to as a serializer-deserializer (SerDes) core, which can subsequently be incorporated into a multi-function chip. At a transmitting end of a serial link, the transmitter of a SerDes core takes a set of parallel data signals at a moderate switching speed and converts them to a high switching speed serial signal for transmission to a remote receiver. At the remote end of the link, the receiver portion of the SerDes core receives the high switching speed serial signal and deserializes it back into a set of parallel data signals at a moderate switching speed.
When a serial data signal first arrives at the front end of a receiver from off of the chip, the serial data signal is processed to check whether it represents a valid signal. Then the switching speed and phase of the clock are recovered from the serial data signal. Next, the serial data signal is sampled by the recovered clock to capture the data transmitted therein. The signal obtained by sampling is then latched into the receiver and deserialized to provide a number of parallel output signals.
The steps of clock recovery and sampling to recover the transmitted data presume the existence of a valid serial data signal, as distinguished from a loss-of-signal condition. Unless the conductors attached at the input to the receiver are carrying a “good” serial data signal, resources and time could be wasted by the receiver processing invalid or unreliable input. Furthermore, invalid data has the potential of causing system errors.
It is therefore desirable for high-speed serial data receivers to have a signal detecting apparatus to quickly and reliably distinguish a “good” serial data signal from a “bad” one. A “bad” signal can occur, for example, when conductors, e.g. a pair of conductors of a coaxial cable, that carry a signal are unintentionally disconnected, such being referred to as “loss-of-line”. A “bad” signal can also occur if the signal conductors become damaged or temporarily interrupted. “Bad” signals also occur when there are voltage or current spikes on the signal conductors, as may be caused by cross-talk or inductive or capacitive coupling from interfering sources. At such times, the magnitude of the incoming signals to the receiver is lower than the low signal limit defined by the customer specification.
When loss-of-signal occurs, some types of receivers that are equipped with an automatic gain control (AGC) loop incorporated with a decision feedback equalizer (“DFE”) feature may incorrectly attempt to restore the signal by increasing the gain at the receiver's front end. In such a case, instead of finding and recovering a good data signal, the receiver might instead amplify the cross-talk noise that appears on the input signal conductors and then proceed in attempting to receive that noise as the transmitted signal. In order to avoid such outcome, it is important for the receiver to detect when the input signal is bad as early as possible. It is desirable that the receiver detects a loss-of-signal condition immediately such that an incoming data packet can be dropped and retransmission of the packet can then be requested. Such operation is critical to maintain the throughput and reliability that are needed when the receiver is used, for example, in security, banking, trading and other such industries.
Various approaches have been taken in prior art systems to determine a loss-of-signal condition. For example, in the article “A Novel High Speed CMOS Signal Transition Detector Circuit,” Research Disclosure, Apr. 16, 2001, a comparator having an offset is used to determine whether the input signal has moved by a predetermined amount away from its quiescent state. If the input signal is transitioning, the detector concludes that the input signal is valid. Otherwise, if the input signal is not transitioning, the detector concludes that the input signal is not valid. However, the system disclosed in that article is not robust, possibly falsely detecting a good signal when a voltage or current spike appears, and having difficulty detecting valid signals in systems having a serial data transmission rate of 5 Gbs and higher.
In another system described in U.S. Pat. No. 6,377,082 B1 (hereinafter “the '082 patent”) issued Apr. 23, 2003 to Loinaz et al., a signal detector includes (1) a transition detector for detecting stuck-on-one and stuck-on-zero loss-of-signal (L-O-S) conditions, and (2) an inconsistency detector for detecting random and undersized signals. A disadvantage of the system described in the '082 patent is that it cannot proceed without having recovered a good clock from the input data signal at the beginning of a data communication period. Hence, the input data signal must be known to be a good signal at the beginning of the data communication period in order for the clock to be recovered. The recovered clock is thereafter used to sample the input data signal in each of two different decision circuits to provide intermediate outputs for deciding whether the input data signal is valid. However, if the input signal is bad from the beginning, the clock may not be present or may be unreliable and incapable of accurately sampling the input signal, making the loss-of-signal detector fail to work at all.
Another problem of the system described in the '082 patent is that it only permits a fixed signal threshold level setting for detecting loss-of-signal. However, it is desirable for a SerDes core to operate according to multiple different specifications and support multiple different speeds and operating voltages. As a result, in communication systems using SerDes cores, a good signal threshold for one system can sometimes resemble noise in others.
In another system, described in U.S. Pat. No. 6,246,268 B1 to Cheng, issued Jun. 12, 2001 (herein after “the '268 patent”) a CMOS signal detection circuit includes (1) a low-pass filter, (2) a high-pass filter, (3) a built-in offset generator and a (4) comparator. The CMOS signal detection circuit is designed to detect an incoming differential signal within a certain frequency range and signal strength. Signals having a predetermined frequency between the cutoff frequencies of the high pass filter and low pass filter are passed to a comparator element of the detector. In the comparator, only signals strong enough to overcome a built-in offset of the comparator result in an output detection signal. As in the above system described in the '082 patent, this system also cannot operate over the wide range of signal frequencies and voltage levels that are desirable for SerDes cores.
In view of the above a robust signal detector that can detect the presence and absence of input signals within a predetermined time interval is needed.